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TDA7415CB
Car radio multimedia signal processor (CMSP)
Features

6-channel multimedia approach Fully integrated tone control with notch filter 7-band spectrum analyzer
Inputs

Three independent signal paths Eight single-ended inputs Two quasi-differential inputs Optional full-differential input Level adjust gain-stages Independent soft-mute and direct-mute
TQFP64
Description
The TDA7415CB is the first 6-channel multimedia approach in the car-radio signal processor (CSP) family. It features full software programmability of three independent sections. The signal processor combines a three band audio tone control with an additional notch filter, high/low pass filters for subwoofer support and a spectrum-analyzer with the absence of any external components for the internal filters. Versatile input/output stages and an extended signal routing scheme provide all the flexibility that is needed to serve modern 6-channel applications such as required by DVD technology.
Outputs

Three independent signal paths Six output channels with soft-step volume Output level up to 4VRMS Independent soft-mute and direct-mute Flexible phone/navigation interrupts High-pass & subwoofer low-pass filters
Digital control
Selectable SPI- or I2C-bus interface Device summary
Temp range, C -40 to 85 Package TQFP64 (10x10x1.4mm) Packing Tray
Table 1.
Order code TDA7415CB
October 2007
Rev 1
1/50
www.st.com 1
Contents
TDA7415CB
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 ESD: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 4.2 4.3 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Main signal processing path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus & control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC Offset Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
Description of the audio processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 5.2 Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Main signal processing path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.1 5.2.2 5.2.3 5.2.4 Bass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Mid filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Treble filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Room EQ filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3
Output path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.1 5.3.2 5.3.3 5.3.4 High pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Low pass (subwoofer) filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Line driver output stage (presenting the reference concept) . . . . . . . . . 28 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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TDA7415CB
Contents
5.4 5.5
Spectrum analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC offset detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6
Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1 6.2 Interface in SPI -mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I2C bus interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8 9 10
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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List of tables
TDA7415CB
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Main signal processing path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus & control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC offset detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Interface in SPI -mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Subaddress allocation (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Main signal path input (addr. 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Main signal path, bass-filter (addr. 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Main signal path, bass-filter (addr. 02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Main signal path, mid-filter (addr. 03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Main signal path, treble-filter (addr. 04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Main signal path, room-EQ (addr. 05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Input section, signal paths A-C (addr. 06-08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Input section; other settings (addr. 09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output section, signal path 0 (addr. 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Output section, signal path 1 and 2 (addr. 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Output section, high-pass filters (addr. 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Output section, volume 0L, 0R, 1L, 1R, 2L, 2R (addr. 13-16, 18, 19) . . . . . . . . . . . . . . . . 42 Output section, subwoofer low-pass filter (addr. 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Output section, bus-mutes (addr. 20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DC-detector and other output section settings (addr. 21) . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Soft-mute and soft-step fader time (addr. 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Spectrum analyzer settings (addr. 23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Testing * (addr. 31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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TDA7415CB
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal-flow input-section (the following soft-mute and output buffer are not shown) . . . . . 18 Bass control range; fC= 60Hz, Q= 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bass center frequencies; gain= 15dB, Q= 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bass filter quality factors; fC= 60Hz, gain= 15dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bass DC-mode frequency responses; gain= 15dB, Q= 1.5 . . . . . . . . . . . . . . . . . . . . . . . . 21 Mid control range; fC= 1kHz, Q= 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Mid center frequencies; gain= 15dB, Q= 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Mid filter quality factors; fC= 1kHz, gain= 15dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Treble control range; fC= 12.5kHz, Q= 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Treble center frequencies; gain= 15dB, Q= 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Room-EQ control range; fC= 200Hz, Q= 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Room-EQ notch frequencies; attenuation= -7dB, Q= 1.0. . . . . . . . . . . . . . . . . . . . . . . . . . 24 Room-EQ notch filter quality factors; fC= 200Hz, attenuation= 7dB.. . . . . . . . . . . . . . . . . 25 Signal flow output section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 High-pass corner frequencies; Q= 0.707 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Low-pass corner frequencies; Q= 0.707. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Line-driver output with reference generation scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Soft-mute signal envelope versus time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Spectrum analyzer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Read cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DC-offset detection circuit (simplified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Switching characteristics (SPI-mode): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Interface in SPI -mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I2C bus interface diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical application connections diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TQFP64 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5/50
Block diagram
TDA7415CB
1
Figure 1.
Block diagram
Block diagram
6/50
TDA7415CB
Pin description
2
2.1
Pin description
ESD:
All pins are protected against ESD according to the MIL883 standard.
2.2
Thermal data
Table 2.
Symbol
Thermal data
Description Value 50 Unit C/W
Rth j-pins Thermal resistance junction-pins
2.3
Pin assignment
Figure 2. Pin connection (top view)
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Pin description
TDA7415CB
2.4
Pin function
Table 3.
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Pin description
Direction
(1)
Name CDCh L CDCh Common CDCh R AUX L AUX Common AUX R MUXA L MUXA R MUXB L MUXB R MUXC L MUXC R WinIn WinTC0 WinTC1 DCErr SEL SDA SCL SAclk SAres. SAout SAin Ref5V5 VolIn L VolIn R Ref3V3 Mute0 Mute1 Mute2 ACout L
Description CD-changer input, pseudo differential, left channel CD-changer input, pseudo differential common CD-changer input, pseudo differential, right channel Aux./Navigation input, pseudo differential, left channel Aux./Navigation input, pseudo differential common Aux./Navigation input, pseudo differential, right channel IN-Section, signal path A output (Main), left channel IN-Section, signal path A output (Main), right channel IN-Section, signal path B output (Sub), left channel IN-Section, signal path B output (Sub), right channel IN-Section, signal path C output (Aux.), left channel IN-Section, signal path C output (Aux.), right channel Zero-window Sense input (from power-amp) Zero-window comparator 0 time constant Zero-window comparator 1 time constant DC-detector Error output Interface-select; SPI: receive enable I2C/SPI-bus serial data input/output I2C/SPI-bus serial clock input Spectrum analyzer clock input Spectrum analyzer reset Spectrum analyzer analog voltage output Spectrum analyzer external input 5.5V-reference decoupling pin, connects to external capacitor Main signal path input, left channel Main signal path input, right channel 3.3V-reference decoupling pin, connects to external capacitor OUT-section, signal path 0 (front) direct mute OUT-section, signal path 1 (rear) direct mute OUT-section, signal path 2 (other) direct mute Main signal path output, left channel
I I I I I I O O O O O O I P P O I I / OC I I I O I P I I P I I I O
8/50
TDA7415CB Table 3.
PIN 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Pin description Pin description (continued)
Direction
(1)
Name ACout R ACin3 R ACin3 L ACin2 R ACin2 L ACin1 R ACin1 L ACin0 R ACin0 L VCC GND LDout2 R LDout2 L LDout1 R LDout1 L PGND PREF LDout0 R LDout0 L VP PAout1 R PAout1 L PAout0 R PAout0 L Mute C Mute B Mute A Tuner L Tuner R CD L CD R MD L MD R
Description Main signal path output, right channel OUT-section, AC-coupled input 3, right channel OUT-section, AC-coupled input 3, left channel OUT-section, AC-coupled input 2, right channel OUT-section, AC-coupled input 2, left channel OUT-section, AC-coupled input 1, right channel OUT-section, AC-coupled input 1, left channel OUT-section, AC-coupled input 0, right channel OUT-section, AC-coupled input 0, left channel Device supply pin Device ground pin Line-driver output, signal path 2 (other), right channel Line-driver output, signal path 2 (other), left channel Line-driver output, signal path 1 (rear), right channel Line-driver output, signal path 1 (rear), left channel Device ground pin (dual supply), connects to system ground Line-driver-reference decoupling pin, connects to external capacitor Line-driver output, signal path 0 (front), right channel Line-driver output, signal path 0 (front), left channel Device supply pin (dual supply), Output section Out-section rear output, right channel Out-section rear output, left channel Out-section front output, right channel Out-section front output, left channel IN-section, signal path 2 (Aux.) direct mute IN-section, signal path 1 (Sub) direct mute IN-section, signal path 0 (Main) direct mute Tuner input, left channel Tuner input, right channel CD input, left channel CD input, right channel Minidisk (mono-differential Phone+) input, left channel Minidisk (mono-differential Phone-) input, right channel
O I I I I I I I I S S O O O O S P O O S O O O O I I I I I I I I I
1. I= input, O= output, OC =open collector, P= passive external component, S= supply
9/50
Features
TDA7415CB
3
Features
The TDA7415CB is composed of four major building blocks. - The IN-section, the spectrumanalyzer, the main signal processing path and the OUT-section; Individually featuring:
IN-section

Three independent signal-paths (front, rear and auxiliary) with independent soft-mute. Six stereo inputs; 3 single ended; 1 single ended or full differential mono; 2 quasidifferential. 15dB level-adjust with 1dB steps. Pin-accessible and/or I2C/SPI-controlled soft-mute (direct mute) for each signal path.
Spectrum-analyzer

7-band, fully integrated 2nd-order band-pass filters with programmable filter quality for different visual behavior. Dedicated one or two-wire serial port for analog data-readout. Analog output voltage 3,3V-P compatible.
Main signal processing path

15dB level-adjust with 1dB steps. Fully integrated bass-, middle- and treble-tone control. All filters offer 2nd-order frequency response with programmable filter quality and center frequency. Room-acoustics notch filter (Room-EQ) allows the suppression of primary car-body resonance.
OUT-section

Three independent signal-paths (front, rear and others) with individual soft-mute. Four AC-coupled, single ended stereo inputs. Pin-accessible soft-mute (direct mute), for each signal path. I2C/SPI-controlled soft-mute, independent for all six (mono) channels Main signal path monitor-select (pre/post tone control). L/R-channel independent phone, navigation or phone/navigation-mix signal interrupts for front signal path; L/R-channel independent phone or navigation interrupts for rearand others-path. 2nd-order frequency response high-pass filters for front- and rear-signal path. 2nd-order frequency response subwoofer low-pass filter for others-signal path. Soft-step volume with 79 to 25dB range for each signal path. Four dedicated outputs for an internal (on-board) power amplifier. Six 4VRMS line-driver outputs for an external (remote) power amplifier. Offset voltage detection circuit for on-board power amplifier failure diagnosis.

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TDA7415CB
Electrical specification
4
4.1
Electrical specification
Supply
Table 4.
Symbol VCC VP Itotal SVRR
Supply
Parameter Supply Voltage Supply Current (Line Driver) Total Supply Current Ripple Rejection @ 1kHz VCC = 8.5V; VP = 12V Audio Processor (all Filters flat) Test conditions Min. 7.5 7.5 Typ. 8.5 12 45 60 Max. 9.5 13 Unit V V mA dB
4.2
Absolute maximum ratings
Table 5.
Symbol VCC VP Tamb Tstg
Absolute maximum ratings
Parameter Operating Supply Voltage Operating Supply Voltage Operating Temperature Range Storage Temperature Range Value 10 13 -40 to 85 -55 to +150 Unit V V C C
4.3
4.3.1
Electrical characteristcs
Input section
VCC = 8.0V; VP = 12.0V; Tamb = 25C; RL =10k ; all gains = 0dB; f = 1kHz; unless otherwise specified. Input section
Parameter Test conditions / remark Single-ended inputs Min. 70 70 35 1.4 2.0 40 40 Typ. 100 100 56 1.5 2.2 70 60 Max. 130 130 65 Unit k k k VRMS VRMS dB dB
Table 6.
Symbol
Rin
Input Impedance
Differential inputs MD-input, differential mode
VCL
Input Clipping Level (THD 0.1%) Common Mode Rejection Ratio Differential inputs (CD, AUX.)
Single ended inputs Differential inputs;
(1)
VCM = 1VRMS @ 1kHz VCM = 1VRMS @ 10kHz
CMRR
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Electrical specification Table 6.
Symbol
TDA7415CB
Input section (continued)
Parameter Common Mode Rejection Ratio Mono differential input (MD) Input Separation Min. Input Gain Max. Input Gain Gain-adjust Step Resolution Adjacent Gain Steps DC-Offset Steps GMIN to GMAX Mute Attenuation T1 80 0.1 0.25 7 16 5 100 0.24 0.48 10.2 20.4 8 1.4 1.0 10 24 3.1 3.3 100 3.5 1.5 0.4 0.75 13 26 15 35 mV dB ms ms ms ms V VRMS k nF V input to output, (1) Test conditions / remark VCM = 1VRMS @ 1kHz VCM = 1VRMS @ 10kHz Min. 40 40 80 -16 14 0.5 Typ. 66 56 100 -15 15 1 0.5 -14 16 1.5 6 Max. Unit dB dB dB dB dB dB mV
CMRRMD SIN GIN MIN GIN MAX GSTEP VDC ATTMUTE
tSMC
Soft-mute completion time, ramp-up or -down
T2 T3 T4
VNO VOUT,max RL CL ROUT VDC
Output-noise, MUX-Outputs Maximum output level Output load resistance Output load capacitance Output impedance DC voltage level
20Hz - 20kHz; all flat, 0dB RLOAD 2k; THD 0.1% THD 0.1%
Spectrum Analyzer (see figure 21) Rin VSAin VSAout fC1 fC2 fC3 fC4 fC5 fC6 fC7 Qf fSAclk tSAdel Input impedance Max. Input level, SAin-pin Output Voltage Range Center Frequency, band 1 Center Frequency, band 2 Center Frequency, band 3
(2) (2) (2)
70 3.3V full scale at SAout-pin RLOAD 1M; VSAin 1VRMS 0 55 141 356 0.9 2.26 5.70 14.4 Q1 Q2 1.40 2.80 1 CLoad at SAout-pin 100pF
100 1.0 62 157 396 1 2.51 6.34 16.0 1.75 3.5
130
k VRMS
3.3 69 173 436 1.1 2.76 6.98 17.6 2.10 4.20 100
V Hz Hz Hz kHz kHz kHz kHz
Center Frequency, band 4 (2) Center Frequency, band 5 Center Frequency, band 6 Center Frequency, band 7 Filter Quality Factor (2) Read-out clock frequency Analog output delay time
(2) (2) (2)
kHz s
1
2
12/50
TDA7415CB Table 6.
Symbol trepeat tintres tSAres
Electrical specification
Input section (continued)
Parameter Read-out cycle repeat time Internal reset time Reset pulse width Test conditions / remark Recommended refresh rate Auto-reset mode enabled Auto-reset mode disabled Min. 50 3 500 4 5 Typ. Max. Unit ms ms ns
1. All differential inputs or differential configurations have -3dB input gain.
4.3.2
Table 7.
Symbol Rin VCL GIN MIN GIN MAX GSTEP VDC VOUT,max RL COUT ROUT VDC
Main signal processing path
Main signal processing path
Parameter Input Impedance Input Clipping Level Min. Input Gain Max. Input Gain Gain-adjust Step Resolution Adjacent Gain Steps DC-Offset Steps GMIN to GMAX Maximum output level Output load resistance Output load capacitance Output impedance DC voltage level 3.1 24 3.3 RLOAD 2k; THD 0.1% THD 0.1% 1.4 1.0 10 36 3.5 5 1.5 30 mV VRMS k nF V THD 0.1% input to output; all filters flat Test conditions / remark Min. 35 1.4 -16 14 Typ. 50 1.5 -15 +15 1 0.5 6 -14 16 Max. 65 Unit k VRMS dB dB dB mV
Bass Control GRANGE ASTEP Gain Control Range Step Resolution fC0 fC1 fC2 fC Center Frequency (1) fC3 fC4 fC5 fC6 fC7 13 0.5 30 40 50 60 60 80 100 120 15 1 40 50 60 70 80 100 120 150 17 1.5 50 50 70 90 100 120 140 170 dB dB Hz Hz Hz Hz Hz Hz Hz Hz
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Electrical specification Table 7.
Symbol
TDA7415CB
Main signal processing path (continued)
Parameter Q1 Test conditions / remark Min. 0.9 1.13 1.35 1.8 -1 3.5 Typ. 1 1.25 1.5 2 0 4.4 Max. 1.1 1.38 1.65 2.2 1 5.5 Unit dB dB
QBASS
Quality Factor (1)
Q2 Q3 Q4 DC-mode= off
DCGAIN MID control GRANGE ASTEP
Bass DC-Gain DC-mode= on
Gain Control Range Step Resolution fC1
13 0.5 450 0.9 1.35 1.8 0.5 1.8
15 1 500 1 1.5 2 1 2
17 1.5 550 1.1 1.65 2.2 1.1 2.2
dB dB Hz kHz kHz kHz
fC
Center Frequency (2)
fC2 fC3 fC4
QMID
Quality Factor (2)
Q1 Q2
Treble Control GRANGE ASTEP Gain Control Range Step Resolution fC1 fC Center Frequency (1)) fC2 fC3 fC4 ROOM-EQ (Acoustics Notch-filter) GRANGE ASTEP Gain Control Range Step Resolution Non-uniform, see description fN1 fC Notch Frequency (1) fN2 fN3 fN4 QEQ Quality Factor(1) Q1 Q2 1 162 180 198 216 0.9 1.8 -0...9 180 200 220 240 1 2 2 198 220 242 264 1.1 2.2 dB dB Hz kHz kHz kHz 13 0.5 6.4 8.0 9.6 11.2 15 1 10 12.5 15 17.5 17 1.5 13.6 17 20.4 23.8 dB dB kHz kHz kHz kHz
1. Min and Max values are calculated according to simulation results; Functionality is guaranteed by measuring a directly correlated parameter
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TDA7415CB
Electrical specification
4.3.3
Output section
VCC = 8.0V; VP = 12.0V; Tamb = 25C; RL =10k ; all gains = 0dB; f = 1kHz; unless otherwise specified Output section
Parameter Input Impedance Input Clipping Level Test conditions AC0...3 inputs THD 0.1% T1 Min. 35 1.4 80 T2 T3 T4 Typ. 50 1.5 100 0.24 0.48 10.2 5.1 Max. 65 Unit k VRMS dB ms ms ms ms
Table 8.
Symbol Rin VCL
ATTMUTE Mute Attenuation Soft-mute completion time, ramp-up or -down
tSMC
Volume (Soft-step) GMAX AMAX ASTEP EA ET VDC High Pass fC0 fC1 fC2 fC Center Frequency
(1)
Max. Gain Max. Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps Adjacent Attenuation Steps From 0dB to GMIN G= -20 to +20dB G= -20 to -60dB -82 0.5 -1.25 -3
25 -79 1 0 0 0.1 0.5 -76 1.5 +1.25 3 2 3 5
dB dB dB dB dB dB mV mV
34 52 72 90 108 135 162 198 0.665
40 60 80 100 120 150 180 220 0.707
46 68 88 110 132 165 198 242 0.750
Hz Hz Hz Hz Hz Hz Hz Hz -
fC3 fC4 fC5 fC6 fC7
QHP
Quality Factor
(2)
Butterworth characteristics
Subwoofer Low Pass fC0 fC1 fC Center Frequency
(2)
44 54 72 90 108 0.665
50 60 80 100 120 0.707
56 66 88 110 132 0.750
Hz Hz Hz Hz Hz -
fC2 fC3 fC4
QHP
Quality Factor
(2)
Butterworth characteristics
Audio Outputs VPA,max Max. output level; PA-outputs RLOAD 2k; THD 0.1% 1.88 2 VRMS
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Electrical specification Table 8.
Symbol VLD,max RL CL ROUT VDC
TDA7415CB
Output section (continued)
Parameter Max. output level; LD-outputs Output load resistance Output load capacitance Output impedance DC voltage level Test conditions as above; VCC = 8.0V as above; VP = 12V THD 0.1%; all outputs All outputs All outputs PA-outputs LD-outputs 3.8 VP / 2 -200mV 24 4.0 VP / 2 Min. 2.20 3.75 1.0 10 100 4.2 VP / 2 +200mV Typ. 2.75 4 Max. Unit VRMS VRMS k nF V V
1. All differential inputs or differential configurations have -3dB input gain. 2. Min and Max values are calculated according to simulation results; Functionality is guaranteed by measuring a directly correlated parameter
4.3.4
Table 9.
Symbol
General
General
Parameter Test Conditions / remark BW = 20Hz to 20KHz unveighted output mode all flat, 0dB Min. Typ. 10 12 110 84 0.01 0.05 80 AV = 0 to -20dB AV = -20 to -60dB Internal POR Voltage 100 0 0 1 2 3.4 0.1 0.1 Max. 15 20 Unit V V dB dB % % dB dB dB V
VNO
Output Noise
all flat, 0dB; VO= 1.5VRMS S/N Signal to Noise Ratio All tone filters +10dB; A-weighted; VO= 1.5VRMS VOUT= 1VRMS; all stages 0dB d Distortion All tone filters +10dB; A-weighted; VO= 1.5VRMS
SC ET VPOR
Channel Separation L/R Total Tracking Error
4.3.5
Table 10.
Symbol VIL VIH VTH VTH
Bus & control inputs
Bus & control inputs (I2C/SPI, spectrum analyzer, direct-mute, offset detector)
Parameter Input Low Voltage Input High Voltage Input threshold voltage Input threshold hysteresis SAres-, SAclk-, all Mute-pins Test conditions / remark SDA-, SCL-, SEL-, WinIn-pin 2.5 Min. Typ. 0.8 2.4 1.5 100 Max. 0.7 Unit V V V mV
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TDA7415CB Table 10.
Symbol IIN VTH,SPI VO,ACK RPULLUP IPULLUP fSCKmax
1. pull-up is needed for I C Mute
2
Electrical specification
Bus & control inputs (continued) (I2C/SPI, spectrum analyzer, direct-mute, offset detector)
Parameter Input Current SPI-mode threshold voltage SDA-Acknowledge Output Volt. Pull-up resistance Pull-up current Maximum clock speed Test conditions / remark VIN= 0.4V; SDA-, SCL-pin
(1)
Min. -5
Typ.
Max. 5 5.5 0.4
Unit A V V k A kbit/s kbit/s
IO= 1.6mA WinIn-pin VIN= 0V, all Mute-pins SPI-mode I
2C-mode
30 50
50 100
70 150 2000 800
4.3.6
Table 11.
Symbol
DC Offset Detector
DC offset detector
Parameter V1 V2 Test conditions / remark Min. Typ. 25 50 75 100 7.5 15 22.5 30 1 2.5 2.5 5 5 3.3 150 300 10 7.5 Max. Unit mV mV mV mV s s s s A mA V mV
Vth
Zero Comp. Window Size V3 V4 1
sp
Max. Rejected Spike Length
2 3 4
IErr,charge IErr,discharge VOutH VOutL
DCErr charge current DCErr discharge current DCErr high voltage DCErr low voltage
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Description of the audio processor
TDA7415CB
5
Description of the audio processor
As can be seen from the block diagram in Figure 1, the Audio processor is composed of three building blocks. - The INPUT-Section, the MAIN-SIGNAL-PROCESSING-path and the OUTPUT-Section. This chapter will give more insight into the different blocks and describe their function.
5.1
Input section
The Input-Section of the TDA7415CB incorporates three independent stereo signal paths, where each can connect to a variety of inputs and the AC3 input from the Output-section for monitoring purposes. For simplicity only the left inputs are shown. After selection by the Main-, Sub-, and/or Auxiliary-source selector, the signal passes a gain-adjust amplifier, a soft-mute stage and finally a buffer before it is output at the device output-pins. The soft-mute circuit will be described later. Figure 3. Signal-flow input-section (the following soft-mute and output buffer are not shown)
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TDA7415CB
Description of the audio processor
The CD-Changer- and Auxiliary/Navigation-inputs are quasi-differential inputs, where the 'out-of-phase' or ground signals of both channels share one common input. The Minidiskinput (MD) may be reconfigured for a true mono differential input as required by many phone units. Please note that all differential inputs dampen the signal by 3dB. Additionally, each differential input-pin features a 'fast charge'-switch (*) allowing quickly charging external, large coupling capacitors upon power-on of the device. For normal operation, these switches need to be released by programming the corresponding bit. For programming of the Input-section, see the programming chapter
5.2
Main signal processing path
The main-signal-processing path incorporates a classical three-band tone control (bass, mid and treble) that is preceded by a gain-adjust amplifier and completed by a dedicated room acoustics notch-filter (Room-EQ, see figure 1) that allows defeating the main car-body resonance. Hereafter, the filters composing the tone control and room-EQ will be presented.
5.2.1
Bass filter
There are four parameters programmable in the bass-filter stage. 1. Control Range: Figure 4 shows the control range in the frequency domain at 60Hz center frequency. Bass control range; fC= 60Hz, Q= 1.0
Figure 4.
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Description of the audio processor 2.
TDA7415CB
Center frequency: Figure 5 shows all the selectable center frequencies at a gain of 15dB Bass center frequencies; gain= 15dB, Q= 1.0
Figure 5.
3.
Quality Factor: Figure 6 shows the four selectable filter quality factors at a gain of 15dB Bass filter quality factors; fC= 60Hz, gain= 15dB.
Figure 6.
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TDA7415CB 4.
Description of the audio processor DC-mode: Figure 7 shows the effect of the DC-mode at a filter gain of 15dB. In this mode the DC-gain is increased by 4.4dB. In addition the programmed center frequencies and quality factors are decreased by 25%, which realizes alternative frequency responses. Bass DC-mode frequency responses; gain= 15dB, Q= 1.5
Figure 7.
5.2.2
Mid filter
There are three parameters programmable in the mid-filter stage. 1. Control Range: Figure 8 shows the control range in the frequency domain at 1kHz center frequency. Mid control range; fC= 1kHz, Q= 1.0
Figure 8.
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Description of the audio processor
TDA7415CB
2.
Center frequency: Figure 9 shows the four selectable center frequencies at a gain of 15dB. Mid center frequencies; gain= 15dB, Q= 1.0
Figure 9.
3.
Quality Factor: Figure 10 shows the two selectable filter quality factors at a gain of 15dB.
Figure 10. Mid filter quality factors; fC= 1kHz, gain= 15dB
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TDA7415CB
Description of the audio processor
5.2.3
1.
Treble filter
There are two parameters programmable in the treble-filter stage. Control Range: Figure 11 shows the control range in the frequency domain at 12.5kHz center frequency.
Figure 11. Treble control range; fC= 12.5kHz, Q= 1.0
2.
Center frequency: Figure 12 shows the four selectable center frequencies at a gain of 15dB
Figure 12. Treble center frequencies; gain= 15dB, Q= 1.0
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Description of the audio processor
TDA7415CB
5.2.4
Room EQ filter
There are three parameters programmable in the room-EQ stage. 1. Control Range: Figure 13 shows the control range in the frequency domain at 200Hz center frequency. The filter has intentional non-uniform attenuation steps. These are 1dB, 2dB, 3dB, 4dB, 5.5dB, 7dB and 9dB.
Figure 13. Room-EQ control range; fC= 200Hz, Q= 1.0
2.
Notch frequency: Figure 14 shows the four selectable notch frequencies at a gain of 15dB
Figure 14. Room-EQ notch frequencies; attenuation= -7dB, Q= 1.0.
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TDA7415CB
Description of the audio processor
3.
Quality Factor: Figure 15 shows the two selectable filter quality factors at a gain of 15dB
Figure 15. Room-EQ notch filter quality factors; fC= 200Hz, attenuation= 7dB.
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Description of the audio processor
TDA7415CB
5.3
Output path
As the Input-Section, the Output-Section of the TDA7415CB incorporates also three independent stereo signal paths, where each can connect to two out of four AC-coupled, single-ended inputs and to some dedicated signals originating from the input-section and/or main-signal-path. For simplicity only one channel is shown in Figure 16. Interruption switches follow the input selectors that can quickly toggle to the phone-, navigation-, or phone/navigation-mix signal independently for each signal path and single L/R-channel. The pre-selection of the interrupt source is common for all signal paths.
Figure 16. Signal flow output section
Signal path 0 and 1 (front and rear) may optionally enter high-pass filters whereas signal path 2 (other) can be low-pass filtered for subwoofer applications. Anti-radiation filters are integrated for all signal paths but there are no anti-alias filters present at the inputs, since for most signal sources it is unlikely to introduce significant high frequency energy. However, if present, the system designer must take care to filter out high frequency components by means of an external RC-low-pass filter located at the AC-input pins. Soft-mute stages and a soft-step volume, that offer fast and click-less muting and/or volume changing follow all three filters. The soft mute circuit will be described later. Five stereo pairs of output buffers finally complete the Output-section: Signal-path 2 exclusively feeds a line driver output that is capable of 4VRMS output level as required by external (remote) power amplifiers. The other signal-paths 1 & 2 feature both, a line driver output and a dedicated internal (on board) power amplifier output with 3dB fixed gain. To maximize the line-driver output swing, when the dual-supply option (VCC = 9V, VP = 12V) is
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TDA7415CB
Description of the audio processor
not needed or available, the line-driver output stages may be programmed for lower gain, still delivering 2.75VRMS. For programming of the Output-section, see the programming chapter Hereafter, the different circuits composing the Output-section will be presented.
5.3.1
High pass filter
1. Corner frequency: Figure 17 shows all the selectable corner frequencies for the highpass filter
Figure 17. High-pass corner frequencies; Q= 0.707
5.3.2
Low pass (subwoofer) filter
1. Corner frequency: Figure 18 shows all the selectable corner frequencies for the lowpass filter.
Figure 18. Low-pass corner frequencies; Q= 0.707
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Description of the audio processor
TDA7415CB
Remark:
Both filters offer a 'Butterworth' roll-off response
5.3.3
Line driver output stage (presenting the reference concept)
In order to adapt to two different supply-voltages for the dual-supply option, while maintaining the highest possible output swing when only a single supply is available, the line-driver output was realized as differential amplifier biased around the two device references PREF and Vref3V3 (see Figure 19). The output DC-voltage precisely tracks the DC-voltage present at the PREF-pin that is half the VP-supply. However, forcing the PREF pin to any desired value could alter this DC-voltage, neglected the remaining output swing. Figure 19. Line-driver output with reference generation scheme
In a dual-supply application (VCC = 8.5V, VP = 12V) the output gain should be set to 9dB to obtain a 4VRMS output level. For a single-supply application (VCC =VP = 8.5V) there is still an output level of 2.75VRMS obtainable. Consequently, to avoid clipping in the output stages the gain needs to be reduced to 5.5dB. For the programming of the output gain, see the programming chapter. Proper power sequencing is no critical issue for the TDA7415. However, it is recommended that both supply-voltages should follow each other within one diode forward-drop (<1V) before reaching their final value.
5.3.4
Soft mute
As can be seen from the block-diagram in figure 1, there are 6 soft-mute circuits placed inside the TDA7415CB: Three each, in both the Input-section and the Output-section that serve the independent signal-paths. A soft-mute can either be achieved by pulling one of the
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TDA7415CB
Description of the audio processor
six soft-mute pins low (hardware-mute) or by assessing the corresponding programming bits (software-mute). For the In-section, a soft-mute is always stereo for each of the three signal-paths and the bus-triggered mute exactly corresponds to the pin-triggered mute, with the exception that the later is inherently faster in response. This behavior is also true for the Out-section, but here the bus-triggered mute is independent for all six single L/R-channels. All mute-pins have internal pull-ups connected to a 3,3Volts reference that allow the connection to either a 3,3V- or a 5V-microproccessor. Reverse flowing currents are limited to 100A, so that the mute-pins may be driven by both, open-drain or push-pull outputs. The envelope slope of the soft-mute was realized in a special S-shaped curve to soften the mute transitions in the critical regions (see Figure 20). The completion time for full mute / no mute is programmable by I2C/SPI-bus in four different values. Figure 20. Soft-mute signal envelope versus time
Note:
A triggered mute is always completed and cannot be interrupted by a change of the initial mute condition. For the programming of the soft-mute, see the programming chapter.
5.4
Spectrum analyzer
A fully integrated seven-band spectrum analyzer is present in the TDA7415CB (Figure 21). The spectrum analyzer consists of seven band pass filters followed by rectifiers with sample capacitors that store the maximum peak signal level for each band since the last read cycle. This peak signal level can be read by a microprocessor at the SAout-pin. To allow easy interfacing to an analog input-port of a microprocessor, the output voltage at this pin is referred to device ground. Since the output voltage follows the peak level linearly, the microprocessor should take care for a logarithmic conversion (e.g. logarithmic look-up table).
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Description of the audio processor
TDA7415CB
The spectrum analyzer's input signal is either the mono-sum of the stereo MUXA-output or alternatively a signal input at the SAin-pin. In order to have some influence on the visual behavior in a given application the filter quality for all band-pass filters may be programmed for two different qualities, with the higher filter quality creating a faster, more differentiating optical response. If the spectrum analyzer is disabled both, the SAres- and the SAclk-pin should be tied to ground. Figure 21. Spectrum analyzer block diagram
The microprocessor starts a read cycle with a negative going clock edge at the SAclk input. On the following positive clock edges, the stored peak signal level of the band pass filters is subsequently switched to SAout. Each analog output value is valid after the time tSAdel. A reset of the sample capacitors is triggered by either pulling the SAres-pin low any time or by setting-up the spectrum-analyzer for Auto-reset mode. Although not shown in Figure 22, for the Auto-reset mode a reset is generated whenever SAclk remains high for the time tintres. Note that a proper auto-reset requires the clock signal SAclk to be held at high potential and that the reset is not repetitive. Once a reset was triggered, a new read-out cycle should not be initiated before the time trepeat has passed. This allows sufficient settling of the filters. Figure 22 illustrates the read cycle timing of the spectrum analyzer. Figure 22. Read cycle timing diagram
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TDA7415CB
Description of the audio processor
5.5
DC offset detector
Using the DC offset detection circuit (figure 22) an offset voltage difference between the audio power amplifier and theTDA7415CB's PA-outputs can be detected, preventing serious damage to the loudspeakers. The circuit compares whether the signal crosses the zero level inside the audio power at the same time as in the speaker cell. The output of the zerowindow-comparator of the power amplifier must be connected with the WinIn-input of the TDA7415CB. The WinIn-input has an internal pull-up resistor connected to 5,5Volts. It is recommended to drive this pin with open-collector outputs only. To compensate for errors at low frequencies the WinTC0/1-pins are implemented, with external capacitors introducing the same delay = 5k * Cext as the AC-coupling between the TDA7415 and the power amplifier introduces. For the zero window comparators, the time constant for spike rejection as well as the threshold are programmable. For electrical characteristics see page 8. A low-active DC-offset error signal appears at the DCErr output if the next conditions are both true: a) b) All PA-outputs (front and rear) are inside zero crossing windows. The Input voltage VWinIn is logic low whenever at least one output of the power amplifier is outside the zero crossing windows.
After power-on, the external attached capacitor is rapidly charged (fast-charge) to overcome a false indication. The fast mode has to be turned off by a manual release of the fast-charge Figure 23. DC-offset detection circuit (simplified)
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Digital interface
TDA7415CB
6
Digital interface
The TDA7415CB digital interface supports two different protocols: SPI and I2C. To select the I2C-mode the SEL-pin has to be tied to the system supply by means of a 68k -resistor. If the voltage at the SEL-pin falls below 5.5V, the interface switches to SPI-mode. Consequently, the interface is able to work with a microprocessor either supplied by a 3.3V or a 5V power supply. The SPI-mode has to be set and remain static before the device leaves the reset state caused by power-on reset (POR). For details of both protocols refer to the programming section.
6.1
Interface in SPI -mode
Interface protocol - A sub-address (SAx) and
The SPI interface protocol comprises: A sequence of n data bytes (Dy); each consisting of 8 bits. A negative going edge at SEL enables the interface receiving data. The interface accepts both a positive (Cpol=1, Cpha=1; SPI-mode 0) as well as a negative (Cpol=0, Cpha=0; SPImode 3) clocking scheme. However, the data transmitted has to be valid on the rising edges of the serial clock SCL. Figure 24. Switching characteristics (SPI-mode):
Figure 25. Interface in SPI -mode diagram
Tscl
Tsu
Thld
Twh
Twl
Trel
Tsh
SEL SCL SDA SAx,Dy
AC00507
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TDA7415CB Table 12.
Symbol fSCLK Tsu Thld Twh Twl Tscl Trel tr tf Tsh
Digital interface
Interface in SPI -mode
Parameter Serial input clock frequency (SCL) Serial data setup time Serial data hold time Serial clock high time width Serial clock low time width Select (SEL) to clock (SCL) falling setup time Clock (SCL) to select (SEL) rising release time Data rise time Data fall time Chip select high time Min 0,00 40,00 40,00 100,00 100,00 200,00 200,00 200,00 Typ Max 4 2,00 2,00 Units MHz ns ns ns ns ns ns s s s
6.2
I2C bus interface description
Interface Protocol - - - - - a start condition (S) a chip address byte (the LSB bit determines read / write transmission) a subaddress byte a sequence of data (N-bytes + acknowledge) a stop condition (P)
The interface protocol comprises:
Figure 26. I2C bus interface diagram
S = Start ACK = Acknowledge
Auto increment
If bit I in the subaddress byte is set to "1", the auto increment of the subaddress is enabled which is also true for the SPI mode.
Chip-address
For the TDA7415CB the chip address is $8C (10001100).
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Digital interface
TDA7415CB
Reset condition
A power-on reset (POR) is generated whenever the supply voltage falls below 4.5V. After that, the following data is written automatically into all sub-address registers:
MSB 1 1 1 1 1 1 1 LSB 0
The programming after POR is marked bold face / underlined in the programming tables.
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TDA7415CB
Programming
7
Table 13.
MSB I2 0 I1
Programming
Subaddress allocation (receive mode)
LSB DESCRIPTION I0 A4 A3 A2 A1 A0 Unassigned Test Mode 0 1 off on Auto Increment Mode 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 ... 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 ... 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 ... 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ... 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ... 0 1 off on Main signal path input gain adjust Main signal path Bass-filter settings I Main signal path Bass-filter settings II Main signal path Mid-filter settings Main signal path Treble-filter settings Main signal path Room-EQ settings Input section, path A input select & gain adjust Input section, path B input select & gain adjust Input section, path C input select & gain adjust Global Input section settings; Bus contr. mutes Output section, path 0 input select & interrupt Output section, path 1&2 input select & interrupt fC-select high-pass filter signal path 0&1 Output section, path 0 left channel Volume Output section, path 0 right channel Volume Output section, path 1 left channel Volume Output section, path 1 right channel Volume fC-select subwoofer filter, path 2 monitor select Output section, path 2 left channel Volume Output section, path 2 right channel Volume Output section, Bus-controlled mutes Dc-detector settings; PA-mutes; Linedriver gain Softstep & Softmute fade-times Spectrum-analyzer settings --------------------------------------------------------------Unassigned --------------------------------------------------------------Test multiplexer; device clocking 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 30 31 Byte (dec)
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Programming
TDA7415CB
7.1
Table 14.
MSB D7 D6
Data byte specification
The status after power-on reset is marked bold face / underlined in the programming tables. Main signal path input (addr. 00)
LSB FUNCTION D5 D4 D3 D2 D1 D0 Input gain adjust level -15dB -14dB ... -1dB -0dB +0dB +1dB ... +14dB +15dB Unused, do not alter
0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 : 1 1 1 1 : 0 0
0 0 : 1 1 1 1 : 0 0
0 0 : 1 1 1 1 : 0 0
0 1 : 0 1 1 0 : 1 0
Table 15.
MSB D7 D6
Main signal path, bass-filter (addr. 01)
LSB FUNCTION D5 D4 D3 D2 D1 D0 Level 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 0dB 1dB : 14dB 15dB Boost / Cut 0 1 Boost Cut Soft-step 0 1 On Off Quality factor
0 0 1 1
0 1 0 1
1.00 1.25 1.50 2.00
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TDA7415CB Table 16.
MSB D7 D6 D5 D4 D3 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D2 1 D1 1
Programming
Main signal path, bass-filter (addr. 02)
LSB FUNCTION D0 0 Unused, do not alter Center frequency 150Hz 120Hz 100Hz 80Hz 70Hz 60Hz 50Hz 40Hz DC-mode Off On
Table 17.
MSB D7 D6
Main signal path, mid-filter (addr. 03)
LSB FUNCTION D5 D4 D3 D2 D1 D0 Level 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 15dB 14dB : 1dB 0dB Boost / Cut 0 1 Cut Boost Center frequency 0 0 1 1 0 1 0 1 500Hz 1.0kHz 1.5kHz 2.0kHz Quality factor
0 1
1.0 2.0
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Programming Table 18.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7415CB
Main signal path, treble-filter (addr. 04)
LSB FUNCTION D0 Level 15dB 14dB : 1dB 0dB Boost / Cut Cut Boost Center frequency 10kHz 12.5kHz 15kHz 17.5KHz Unused, do not alter
0 0 : 1 1 0 1 0 0 1 1 1 0 1 0 1
0 0 : 1 1
0 0 : 1 1
0 1 : 0 1
Table 19.
MSB D7 D6
Main signal path, room-EQ (addr. 05)
LSB FUNCTION D5 D4 D3 D2 D1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D0 0 Unused, do not alter Attenuation level 9dB 7dB 5.5dB 4dB 3dB 2dB 1dB 0dB Center frequency 240Hz 220Hz 200Hz 180Hz Quality factor 1.0 2.0
0 1
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TDA7415CB Table 20.
MSB D7 D6 D5 D4 D3 D2 D1
Programming
Input section, signal paths A-C (addr. 06-08)
LSB FUNCTION D0 Input gain adjust level -15dB -14dB ... -1dB -0dB +0dB +1dB ... +14dB +15dB Input select Tuner CD MD / Phone CD-Changer (quasi-differential) AUX./Navigation (quasi-differential) Navigation (mono-Mix) AC3in-monitor (from OUT-section) Full mute
0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
0 0 : 1 1 1 1 : 0 0
0 0 : 1 1 1 1 : 0 0
0 0 : 1 1 1 1 : 0 0
0 1 : 0 1 1 0 : 1 0
Table 21.
MSB D7 D6
Input section; other settings (addr. 09)
LSB FUNCTION D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 1 1 0 1 1 Unused, do not alter Soft-mute, signal path A No mute Mute Soft-mute, signal path B No mute Mute Soft-mute, signal path C No mute Mute Unused, do not alter MD-mode Single ended, stereo (e.g. Minidisk) Full differential, mono (e.g. external Phone) Fast-charge (quasi-differential inputs) Release Engage
0 1
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Programming Table 22.
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1
TDA7415CB
Output section, signal path 0 (addr. 10)
LSB D0 0 1 0 1 FUNCTION Input select Main signal path Output select AC0in AC3in Main signal path PRE-Tone select Interrupts select, right channel Not allowed Interrupt enable Interrupt, 50% signal mix Interrupt bypass, normal operation Interrupts select, left channel Not allowed Interrupt enable Interrupt, 50% signal mix Interrupt bypass, normal operation Unused, do not alter Interrupt Pre-select (common for all paths) Navigation Phone
Table 23.
MSB D7 D6
Output section, signal path 1 and 2 (addr. 11)
LSB D5 D4 D3 D2 D1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 D0 0 1 0 1 FUNCTION Input select signal path1 Main signal path Output select AC1in AC3in Main signal path PRE-Tone select Interrupts select, right channel signal path 1 Interrupt enable Interrupt bypass, normal operation Interrupts select, left channel signal path 1 Interrupt enable Interrupt bypass, normal operation Input select signal path2 Main signal path Output select AC2in AC3in Main signal path PRE-Tone select Interrupts select, right channel signal path 2 Interrupt enable Interrupt bypass, normal operation Interrupts select, left channel signal path 2 Interrupt enable Interrupt bypass, normal operation
0 1
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TDA7415CB Table 24.
MSB D7 D6 D5 D4 D3 D2 D1
Programming
Output section, high-pass filters (addr. 12)
LSB FUNCTION D0 Corner frequency, High-pass signal path 0 40Hz 60Hz 80Hz 100Hz 120Hz 150Hz 180Hz 220Hz Bypass, High-pass signal path 0 Filter bypass Filter insert Corner frequency, High-pass signal path 1 40Hz 60Hz 80Hz 100Hz 120Hz 150Hz 180Hz 220Hz Bypass, High-pass signal path 1 Filter bypass Filter insert
0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
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Programming Table 25.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7415CB
Output section, volume 0L, 0R, 1L, 1R, 2L, 2R (addr. 13-16, 18, 19)
LSB FUNCTION D0 Volume level 0 0 0 1 1 1 : 0 0 1 1 : 0 0 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 X 1 : 0 0 0 : 0 0 1 1 : 0 0 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 X 1 : 1 0 0 : 0 0 1 1 : 0 0 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 X 1 : 0 1 0 : 1 0 1 0 : 1 0 0 1 : 0 1 0 1 : 0 1 0 1 : 0 1 0 1 : 0 1 0 1 : 0 1 X Not allowed +25dB +24dB ... +17dB +16dB +15dB +14dB ... +1dB +0dB -0dB -1dB ... -14dB -15dB -16dB -17dB ... -30dB -31dB -32dB -33dB ... -46dB -47dB -48dB -49dB ... -62dB -63dB -64dB -65dB ... -78dB -79dB Mute Soft-step On Off
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1 0 1
1
1
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TDA7415CB Table 26.
MSB D7 D6 D5 D4 D3 D2 D1
Programming
Output section, subwoofer low-pass filter (addr. 17)
LSB FUNCTION D0 0 X X 0 1 X 0 0 0 0 1 1 0 0 1 1 X 1 0 1 0 1 X 1 0 0 1 1 1 0 1 0 0 1 Unused, do not alter Monitor select Signal path 0 (before Soft-mute) Signal path 1 (before Soft-mute) Low-pass filter (Subwoofer enable) Mono-sum bypass Stereo bypass (direct through) Corner frequency 120Hz 100Hz 80Hz 60Hz 50Hz 50Hz Phase No shift Inverted
0 1
Table 27.
MSB D7 D6
Output section, bus-mutes (addr. 20)
LSB FUNCTION D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 1 0 1 0 1 0 1 Unused, do not alter Soft-mute, right channel signal path 0 No mute Mute Soft-mute, left channel signal path 0 No mute Mute Soft-mute, right channel signal path 1 No mute Mute Soft-mute, left channel signal path 1 No mute Mute Soft-mute, right channel signal path 2 No mute Mute Soft-mute, left channel signal path 2 No mute Mute Unused, do not alter
1
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Programming Table 28.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7415CB
DC-detector and other output section settings (addr. 21)
LSB FUNCTION D0 Line drivers gain 9dB 5.5dB PAout0 (front) mute No mute Mute PAout1 (rear) mute No mute Mute DCError output behavior Forced high level by mute; (1) Normal operation, see description Chapter 5.5. Zero-comparator Window size 100mV 75mV 50mV 25mV Spike rejection time constant 11s 22s 33s 44s
0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
1. DCError output high for OUTsection signal paths 1&2 muted or all PAout muted
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TDA7415CB Table 29.
MSB D7 D6 D5 D4 D3 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D2 1 D1 1
Programming
Soft-mute and soft-step fader time (addr. 22)
LSB FUNCTION D0 0 Unused, do not alter Input selection prcedure Soft-mute completion time programmed according to bits D6 and D7 Soft-mute completion time fixed to 0.5ms Soft-step completion time 0.32ms 0.64ms 1.28ms 2.56ms Soft-mute completion time 0.25ms 0.5ms 10ms 5ms
Table 30.
MSB D7 D6
Spectrum analyzer settings (addr. 23)
LSB FUNCTION D5 D4 D3 D2 D1 D0 Run/stop (internal clocking) Stop Run Filter quality High Low Reset mode SAres-pin triggered reset Auto-reset mode Source select Mono-sum of MUXA-outputs SAin-pin Unused, do not alter
0 1 0 1 0 1 0 1 1 1 1 1
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Programming Table 31.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7415CB
Testing * (addr. 31)
LSB FUNCTION D0 0 1 1 1 1 Device clock Enable internal clock generation Allow external clocking in fast-mode Unused, do not alter Test selector
0 0 0 0 1 1 1 1 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
TUNER L out: DCDet., lower TC-Vth Spec.Anal. 60Hz-bandpass Spec.Anal. 160Hz-bandpass Spec.Anal. 400Hz-bandpass Spec.Anal. 1kHz-bandpass Spec.Anal. 2,5kHz-bandpass Spec.Anal. 6,3kHz-bandpass Spec.Anal. 16kHz-bandpass Test mode Enabled * Disabled
TUNER R out: DCDet., upper TC-Vth 5,5V CMOS-supply DCDet., time constant 200kHz reference clock actual Soft-Mute clock actual Soft-Step clock SC-reference, left chan. DC-Offset monitor point
Successfully entering the test-mode requires to set bit D6 of the sub address (test mode-bit) to "1". In test-mode, the TUNER L&R inputs are reconfigured as output for the selected test signals Note: This byte is used for testing and/or evaluation purposes only and must not be set to other values than the default "11111110" in the application.
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TDA7415CB
Application information
8
Application information
Figure 27. Typical application connections diagram
Figure 27 shows a proposal for a typical application. - However, the figure only represents one possible interconnection scheme with other devices (The shaded blocks could represent a complex digital sound reproducing/processing system). For simplicity, this proposal assumes the system designer not to take advantage from the direct muting feature and therefore let the corresponding Mute-pins floating. All capacitor values are suggestions with their dimensioning still being dependant on girdling impedances. This is especially true for the capacitors located at the WinTC-pins as can be read in chapter 6.5. In case the DC-detector function is not assessed in the application it is recommended to short both the WinTC-pins 14 and 15 to device-ground.
68
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Package information
TDA7415CB
9
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 28. TQFP64 mechanical data and package dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K ccc 0.45 11.80 9.80 0.05 1.35 0.17 0.09 11.80 9.80 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 12.20 10.20 0.464 0.386 12.20 10.20 1.40 0.22 TYP. MAX. 1.60 0.15 1.45 0.27 0.002 0.053 0.055 MIN. TYP. MAX. 0.063 0.006 0.057 inch
OUTLINE AND MECHANICAL DATA
0.0066 0.0086 0.0106 0.0035 0.464 0.386 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0177 0.0236 0.0295 0.0393 0.480 0.401 0.480 0.401
0 (min.), 3.5 (min.), 7(max.) 0.080 0.0031
TQFP64 (10 x 10 x 1.4mm)
D D1 A D3 A1 48 49 33 32
0.08mm ccc Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
B
0051434 E
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TDA7415CB
Revision history
10
Revision history
Table 32.
Date 26-Oct-2007
Document revision history
Revision 1 Initial release. Changes
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TDA7415CB
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